1. Field of the Invention
The present invention relates to a semiconductor device having an input protection circuit section or an output protection circuit section between an input/output terminal and an internal circuit to prevent the electrostatic discharge(ESD).
2. Description of the Related Art
In a semiconductor integrated circuit device, an input protection circuit section or an output protection circuit section {referred to as an input/output protection circuit section, hereinafter) is set between an input terminal or an output terminal (referred to as an input/output terminal, hereinafter} and an internal circuit in order to protect circuit elements inside from failure which may be brought about by an ESD or the like applied to the input/output terminal.
An input/output protection circuit section itself is generally composed of CMOSs (Complementary Metal-Oxide-Semiconductor) in each of which an N-channel MOSFET (Field Effect Transistor) and a P-channel MOSFET are connected in series between the supply voltage VDD and the ground voltage GND. FIG. 14 is a diagram of an input protection circuit composed of CMOSs and FIG. 15, a diagram of an output protection circuit composed of CMOSs. Now, referring to the drawings, an example of a conventional input protection circuit section composed as shown in FIG. 14 is described below.
FIG. 6 is a plan view showing a conventional input protection circuit section composed of CMOSs and FIG. 7, a cross-sectional view showing the portion A–A′ of FIG. 6. As shown in FIG. 7, on the surface of a P-type silicon substrate 20, an N-type well 1b and a P-type well 2 is formed. In the region where the P-type well 2 is formed, an N-channel MOSFET comprising a gate electrode 6, a source region 3c and a drain region 3b is formed. In the periphery of the N-channel MOSFET formation area, a P-type dopant diffusion region 4a is set (FIG. 6), and thereby the electric potential of the P-type well 2 is defined. The P-type dopant diffusion region 4a and the source region 3c, set separated by an element isolation film 10, are both connected with a ground terminal 9 (GND). The drain region 3b is connected with an input terminal 7.
Meanwhile, in the region where the N-type well 1b is formed, a P-channel MOSFET comprising a gate electrode 5, a source region 4c and a drain region 4b is formed. In the periphery of the P-channel MOSFET formation area, an N-type dopant diffusion region 3a is set (FIG. 6), and thereby the electric potential of the N-type well 1b is defined. The N-type dopant diffusion region 3a and the source region 4c, set separated by an element isolation film 10, are both connected with a supply terminal 8 (VDD). The drain region 4b is connected with an input terminal 7.
Further, for the purpose of lowering electrical resistance, silicide layers 13 are formed over the surfaces of the source-drain regions and such, in every transistor.
Next, operations that take place on application of an external surge to the input terminal 7 are described. Firstly, operations that the N-channel MOSFET makes when an external surge is applied to the input terminal 7 with a negative voltage with respect to the ground terminal 9 are described. A forward voltage is, in this instance, applied to the PN-junction between the drain region 3b (N-type) and the P-type well 2 and the PN diode is turned on in the forward direction so that the negatively polarized surge flows down from the input terminal 7, through the drain region 3b and the P-type well 2, to the ground terminal 9. Next, operations produced when an external surge is applied to the input terminal 7 with a positive voltage with respect to the ground terminal 9 are described. In this case, a positive voltage with respect to the P-type well of the N-channel transistor is applied to the drain. When this voltage exceeds a certain value, an avalanche breakdown takes place in the vicinity of the drain region 3b. After the breakdown, a current flows from the drain region 3b to the P-type well 2 and this current leads the P-type well 2 to have a positive electric potential, which results in turning-on of an NPN parasitic bipolar transistor in which the drain region 3b, the P-type well 2 and the source region 3c act as a collector, a base and an emitter, respectively. The surge, then, flows from the internal terminal 7, through the drain region 3b, the P-type well 2 and the source region 3c, and consequently to the ground terminal 9. The operations described above are further described with reference to FIG. 9. In FIG. 9, when the drain voltage reaches the breakdown voltage VB, the breakdown takes place and, after that, the voltage rises, up to the trigger voltage Vt1. Once the voltage reaches Vt1, the NPN parasitic bipolar transistor is turned on, and the voltage drops to the snap-back holding voltage VS. When the current and the voltage rise again and reach the value of the current It2 and the value of the voltage Vt2, respectively, the transistor is driven to a failure.
While only operations of the N-channel MOSFET are described so far, the P-channel MOSFET operates in a similar fashion. In short, when an external surge is applied to the internal terminal 7 with a positive or a negative voltage with respect to the supply terminal 8, either the PN junction in the forward direction is turned on, or alternatively, a lateral parasitic bipolar transistor is turned on. In either way, the surge flows down to the supply terminal 8 and thereby the internal circuit is protected.
However, the protection circuit section described above has the following problem, originating from the fact that Vt2 (the transistor failure voltage) is lower than Vt1 (the trigger voltage), as seen in FIG. 9.
The protection circuit section is normally composed of a plurality of transistors, and each transistor has a slightly different own trigger voltage of the snap-back. As a result, when the snap-back operation starts, it is made by not all but only some of the transistors. However, the voltage of the input/output terminal, thereat, falls back to the snap-back holding voltage VS of these transistors, and, then, recovers only up to Vt2 of these transistors. With respect to the rest of the transistors, therefore, the snap-back operation cannot be induced, since the drain voltage does not exceed their own Vt1. In consequence, the surge always flows down only to the transistors making the snap-back operation and leads them to failures, which lowers the protective capability of the protection circuit section. In recent years, with the object of reducing the parasitic resistance and the like, metal silicide films are often formed over the surfaces of the source-drain regions of the transistors and such. In such a case, the surge current is drawn to the vicinity of metal silicide layers of low resistivity so that the above problem becomes more pronounced.
Although the above description is made, with N-channel transistors considered, the similar can be applied to the case of P-channel transistors.
To overcome the above problem, a high-resistance region is often set by the side of the drain region of the transistor. FIG. 10 and FIG. 11 show the protection circuit section disclosed in Japanese Application Laid-open No. 173070/1998. In this protection circuit section, an N-type well 1c is formed by the side of a drain region 3b of an N-channel MOSFET, and a control electrode 6a is set in order to define the electric potential of the N-type well 1c (FIG. 11). With the N-type well resistance 14, the resistance between the input terminal 7 and the ground terminal 9 increases and the relationship between the drain voltage Vds and the drain current Ids becomes the one as shown in FIG. 12. In the drawing, the dotted line represents the profile of the conventional technique and the solid line, the profile of the protection circuit section of FIG. 11. In the profile of the solid line, the value of dIds/dVds between VS and Vt2 is made smaller by the presence of the N-type well resistance 14, and, consequently, Vt2 increases to establish the relationship Vt1<Vt2. Under this condition, even if only some of the transistors are induced to make the snap-back operation first, the rest of the transistors are also induced to make the snap-back operation in the similar fashion, as the drain voltage, after the snap-back, increases from VS to Vt2, and, thus, a plurality of transistors all function alike. Therefore, more than sufficient surge-proof (ESD (Electrostatic Discharge)-proof) can be secured, without lowering protective capability thereof. In this way, the use of a method in which a high-resistance region is set can make a plurality of transistors operate all alike and heighten the reliability of the protection circuit section. Accordingly, the above method is widely utilized for the protection circuit sections. Yet, this method wherein a high-resistance region is formed still has problems in the following points. Firstly, an addition of a high-resistance region lowers the driving capability of the protection circuit section and worsens the quality of high-speed operation thereof. Secondly, as the drain current of the transistor becomes smaller due to the presence of the high-resistance region, the transistor size required to secure a prescribed driving current in the output circuit or the like becomes larger. Thirdly, in order to dispose a resistance element between a gate and a contact in the drain region of the protection circuit section, the spacing between the gate and the drain must be set wider, which hinders the LSI (Large Scale-Integrated circuit) miniaturization.
Meanwhile, for the arrangement of the protection circuit section in the LSI, a form in which a protection circuit section composed of complementary field effect transistors is set between the supply voltage VDD and the ground voltage GND is generally utilized. This arrangement can make a surge flow down to the GND or the VDD efficiently and, therefore, can attain a good ESD-proof and maintain the quality for the protection circuit response.
When the protection circuit section composed of complementary field effect transistors is employed, prevention of latch-up becomes another important technical problem. As a prevention measure of latch-up, it is well known that setting a dopant high-concentration region beneath wells in the transistor formation area is effective (Japanese Patent Application Laid-open No. 321150/1997). FIG. 13 shows an example of the CMOS with such a structure. Nevertheless, when such a structure is employed for the protection circuit section, although the latch-up-proof certainly, improves through a reduction of the shunt resistance, a problem of a decrease in the ESD-proof arises. The explanation lies in the fact that, with reducing the shunt resistance, the current amplification factor of the parasitic bipolar transistor decreases and this makes the parasitic bipolar operation difficult to induce. In effect, this structure has an adverse effect on the protection circuit section that makes use of parasitic bipolar operations. Accordingly, a technique that can improve the latch-up-proof while maintaining the ESD-proof of the protection circuit section has been very much waited for.